1. Field of the Invention
The present invention is directed in general to data communications. In one aspect, the present invention relates to a method and system for improving descriptor based packet processing in microprocessor or multiprocessor computer devices.
2. Related Art
As is known, communication technologies that link electronic devices may use multiprocessor switching devices to route and process signal information. Some communication technologies interface a one or more processor devices for processing packet-based signals in a network of computer systems. Generally, packets are used to communicate among networked computer and electronic systems. Thus, each networked system must receive and transmit packets, and must process the packets directed to that system to determine what is being transmitted to that system.
Typically, each computer system includes one or more interfaces or ports on which packets are transmitted and received. Additionally, each interface generally includes a dedicated DMA engine used to transmit received packets to memory in the system and to read packets from the memory for transmission. If a given system includes two or more packet interfaces, the system includes DMA engines for each interface. Where a computer system processes multiple packet channels using the DMA engines, the processor(s) in the system must be able to monitor the status of the DMA transfers for each channel and other system-related functions associated with the channel transfers.
Conventional systems that use descriptors for DMA transfers typically write back the descriptor to the memory when the DMA engine is done processing the descriptor. In such systems where the descriptor size does not match the memory block size (such as cache memory), the DMA engine in such conventional systems must perform a Read-Modify-Write (RMW) operation in order to write the finished descriptor back to the memory. This requires the DMA engine to wait for reads from the main memory for each RMW operation, thereby degrading the speed and performance of the DMA engine. As the number of channels increases, the unwieldiness of conventional approaches also increases.
Therefore, a need exists for methods and/or apparatuses for improving the processing of descriptor-based packet transfers to quickly and efficiently write packets of data to memory. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.